According to recent provisions of service where broadcasting and communication are integrated, a high-speed network protocol processing is required. As means for speeding-up the network protocol processing and the like, there is an accelerator. When a hardware accelerator is prepared as a peripheral device for a CPU, data transfer between a memory (an external storage device) and a peripheral device (a hardware accelerator) is generally performed by DMA (Direct Memory Access). The DMA transfer is roughly classified to a register direct mode and a chain or ring system.
In hardware accelerators including a DMA device, the maximum data number or the maximum data size which can be processed at a time is fixed due to property thereof. In the DMA device, the number of address registers storing source address or destination address, and a size of a data register (a processing buffer) temporarily storing data transferred to the DMA device are fixed.
Therefore, when an operation for processing an arbitrary number of data is performed in the DMA device, or when a processing required for retaining a large data size is performed in the DMA device, a problem arises. Hereinafter, a hardware accelerator (DMA device) performing a predetermined operation at high speeds using the DMA transfer, which performs an operation on input data obtained by the DMA transfer and output the result is also called as “operational circuit”.
Regarding the abovementioned operational circuit, for example, it is considered to perform FEC operation by hardware implementation. Regarding the FEC, there is a technique disclosed in Non-Patent Document 1 (Rosenberg, J. and H. Schulzrinne, “An RTP Payload Format for Generic Forward Error Correction”, RFC2733, December 1999). In the FEC, since alignment of a transferring packet or an error correction operation must be performed prior to transfer, CPU power is required. It is desired to make protocol processings efficient by realizing the FEC processing by a hardware accelerator (operational circuit).
An accelerator having a structure disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 6-259268 (Patent Document 1) can be applied in order to obtain hardware implementation for the FEC operation because this is an analogous technique. The technique described in Patent Document 1 is a hardware accelerator performing an operation of checksum for error detection of packet data. The FEC and the checksum are each multi-input one-output operation processing for deriving one output from a number of data pieces.